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The Resource A designer's guide to asynchronous VLSI, Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti

A designer's guide to asynchronous VLSI, Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti

Label
A designer's guide to asynchronous VLSI
Title
A designer's guide to asynchronous VLSI
Statement of responsibility
Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti
Creator
Contributor
Subject
Language
eng
Summary
  • "Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications"--Provided by publisher
  • "This book provides an introduction to this diverse area of VLSI from a designer's point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future"--Provided by publisher
Cataloging source
DLC
http://library.link/vocab/creatorName
Beerel, Peter A
Dewey number
621.39/5
Illustrations
illustrations
Index
index present
LC call number
TK7888.4
LC item number
.B44 2010
Literary form
non fiction
Nature of contents
bibliography
http://library.link/vocab/relatedWorkOrContributorName
  • Ozdag, Recep O
  • Ferretti, Marcos
http://library.link/vocab/subjectName
  • Integrated circuits
  • Integrated circuits
Label
A designer's guide to asynchronous VLSI, Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier category code
nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith
Control code
459209613
Dimensions
26 cm
Extent
xii, 339 pages
Isbn
9780521872447
Lccn
2009042290
Media category
unmediated
Media MARC source
rdamedia
Media type code
n
Other physical details
illustrations
System control number
(OCoLC)459209613
Label
A designer's guide to asynchronous VLSI, Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier category code
nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith
Control code
459209613
Dimensions
26 cm
Extent
xii, 339 pages
Isbn
9780521872447
Lccn
2009042290
Media category
unmediated
Media MARC source
rdamedia
Media type code
n
Other physical details
illustrations
System control number
(OCoLC)459209613

Library Locations

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      38.946102 -92.330125
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