The Resource Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings, Thomas Ball, Robert B. Jones (eds.)
Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings, Thomas Ball, Robert B. Jones (eds.)
Resource Information
The item Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings, Thomas Ball, Robert B. Jones (eds.) represents a specific, individual, material embodiment of a distinct intellectual or artistic creation found in University of Missouri Libraries.This item is available to borrow from 2 library branches.
Resource Information
The item Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings, Thomas Ball, Robert B. Jones (eds.) represents a specific, individual, material embodiment of a distinct intellectual or artistic creation found in University of Missouri Libraries.
This item is available to borrow from 2 library branches.
- Language
- eng
- Extent
- 1 online resource (xv, 564 pages)
- Contents
-
- Invited Talks
- Formal Specifications on Industrial-Strength Code--From Myth to Reality
- I Think I Voted: E-Voting vs. Democracy
- Playing with Verification, Planning and Aspects: Unusual Methods for Running Scenario-Based Programs
- The Ideal of Verified Software
- Session 1. Automata
- Antichains: A New Algorithm for Checking Universality of Finite Automata
- Safraless Compositional Synthesis
- Minimizing Generalized Büchi Automata
- Session 2. Tools Papers
- Ticc: A Tool for Interface Compatibility and Composition
- FAST Extended Release
- Session 3. Arithmetic
- Don't Care Words with an Application to the Automata-Based Approach for Real Addition
- A Fast Linear-Arithmetic Solver for DPLL(T)
- Session 4. SAT and Bounded Model Checking
- Bounded Model Checking for Weak Alternating Büchi Automata
- Deriving Small Unsatisfiable Cores with Dominators
- Session 5. Abstraction/Refinement
- Lazy Abstraction with Interpolants
- Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop
- Counterexamples with Loops for Predicate Abstraction
- Session 6. Tools Papers
- cascade: C Assertion Checker and Deductive Engine
- Yasm: A Software Model-Checker for Verification and Refutation
- Session 7. Symbolic Trajectory Evaluation
- SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation
- Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation
- Session 8. Property Specification and Verification
- Some Complexity Results for SystemVerilog Assertions
- Check It Out: On the Efficient Formal Verification of Live Sequence Charts
- Session 9. Time
- Symmetry Reduction for Probabilistic Model Checking
- Communicating Timed Automata: The More Synchronous, the More Difficult to Verify
- Allen Linear (Interval) Temporal Logic
- Translation to LTL and Monitor Synthesis
- Session 10. Tools Papers
- DiVinE
- A Tool for Distributed Verification
- EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation
- Session 11. Concurrency
- Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions
- Model Checking Multithreaded Programs with Asynchronous Atomic Methods
- Causal Atomicity
- Session 12. Trees, Pushdown Systems and Boolean Programs
- Languages of Nested Trees
- Improving Pushdown System Model Checking
- Repair of Boolean Programs with an Application to C
- Session 13. Termination
- Termination of Integer Linear Programs
- Automatic Termination Proofs for Programs with Shape-Shifting Heaps
- Termination Analysis with Calling Context Graphs
- Session 14. Tools Papers
- Terminator: Beyond Safety
- CUTE and jCUTE: Concolic Unit Testing and Explicit Path Model-Checking Tools
- Session 15. Abstract Interpretation
- SMT Techniques for Fast Predicate Abstraction
- The Power of Hybrid Acceleration
- Lookahead Widening
- Session 16. Tools Papers
- The Heuristic Theorem Prover: Yet Another SMT Modulo Theorem Prover
- LEVER: A Tool for Learning Based Verification
- Session 17. Memory Consistency
- Formal Verification of a Lazy Concurrent List-Based Set Algorithm
- Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
- Fast and Generalized Polynomial Time Memory Consistency Verification
- Session 18. Shape Analysis
- Programs with Lists Are Counter Automata
- Lazy Shape Analysis
- Abstraction for Shape Analysis with Fast and Precise Transformers
- Isbn
- 9783540374114
- Label
- Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings
- Title
- Computer aided verification
- Title remainder
- 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings
- Statement of responsibility
- Thomas Ball, Robert B. Jones (eds.)
- Title variation
- CAV 2006
- Subject
-
- Computer software -- Verification
- Computer software -- Verification
- Computer software -- Verification
- Computer software -- Verification -- Congresses
- Conference papers and proceedings
- Conference papers and proceedings
- Informatique
- Integrated circuits -- Verification
- Integrated circuits -- Verification
- Integrated circuits -- Verification
- Integrated circuits -- Verification -- Congresses
- Logiciels -- Vérification
- Circuits intégrés -- Vérification
- Language
- eng
- Cataloging source
- GW5XE
- Dewey number
- 004.24
- Illustrations
- illustrations
- Index
- index present
- Language note
- English
- LC call number
- QA76.76.V47
- LC item number
- C38 2006eb
- Literary form
- non fiction
- http://bibfra.me/vocab/lite/meetingDate
- 2006
- http://bibfra.me/vocab/lite/meetingName
- CAV (Conference)
- Nature of contents
-
- dictionaries
- bibliography
- http://library.link/vocab/relatedWorkOrContributorDate
-
- 1965-
- 1969-
- http://library.link/vocab/relatedWorkOrContributorName
-
- Ball, Thomas
- Jones, Robert B.
- Series statement
-
- Lecture notes in computer science,
- LNCS sublibrary. SL 1, Theoretical computer science and general issues
- Series volume
- 4144
- http://library.link/vocab/subjectName
-
- Computer software
- Integrated circuits
- Integrated circuits
- Circuits intégrés
- Logiciels
- Computer software
- Informatique
- Computer software
- Integrated circuits
- Label
- Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings, Thomas Ball, Robert B. Jones (eds.)
- Bibliography note
- Includes bibliographical references and index
- Carrier category
- online resource
- Carrier category code
-
- cr
- Carrier MARC source
- rdacarrier
- Color
- multicolored
- Content category
- text
- Content type code
-
- txt
- Content type MARC source
- rdacontent
- Contents
- Invited Talks -- Formal Specifications on Industrial-Strength Code--From Myth to Reality -- I Think I Voted: E-Voting vs. Democracy -- Playing with Verification, Planning and Aspects: Unusual Methods for Running Scenario-Based Programs -- The Ideal of Verified Software -- Session 1. Automata -- Antichains: A New Algorithm for Checking Universality of Finite Automata -- Safraless Compositional Synthesis -- Minimizing Generalized Büchi Automata -- Session 2. Tools Papers -- Ticc: A Tool for Interface Compatibility and Composition -- FAST Extended Release -- Session 3. Arithmetic -- Don't Care Words with an Application to the Automata-Based Approach for Real Addition -- A Fast Linear-Arithmetic Solver for DPLL(T) -- Session 4. SAT and Bounded Model Checking -- Bounded Model Checking for Weak Alternating Büchi Automata -- Deriving Small Unsatisfiable Cores with Dominators -- Session 5. Abstraction/Refinement -- Lazy Abstraction with Interpolants -- Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop -- Counterexamples with Loops for Predicate Abstraction -- Session 6. Tools Papers -- cascade: C Assertion Checker and Deductive Engine -- Yasm: A Software Model-Checker for Verification and Refutation -- Session 7. Symbolic Trajectory Evaluation -- SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation -- Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation -- Session 8. Property Specification and Verification -- Some Complexity Results for SystemVerilog Assertions -- Check It Out: On the Efficient Formal Verification of Live Sequence Charts -- Session 9. Time -- Symmetry Reduction for Probabilistic Model Checking -- Communicating Timed Automata: The More Synchronous, the More Difficult to Verify -- Allen Linear (Interval) Temporal Logic -- Translation to LTL and Monitor Synthesis -- Session 10. Tools Papers -- DiVinE -- A Tool for Distributed Verification -- EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation -- Session 11. Concurrency -- Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions -- Model Checking Multithreaded Programs with Asynchronous Atomic Methods -- Causal Atomicity -- Session 12. Trees, Pushdown Systems and Boolean Programs -- Languages of Nested Trees -- Improving Pushdown System Model Checking -- Repair of Boolean Programs with an Application to C -- Session 13. Termination -- Termination of Integer Linear Programs -- Automatic Termination Proofs for Programs with Shape-Shifting Heaps -- Termination Analysis with Calling Context Graphs -- Session 14. Tools Papers -- Terminator: Beyond Safety -- CUTE and jCUTE: Concolic Unit Testing and Explicit Path Model-Checking Tools -- Session 15. Abstract Interpretation -- SMT Techniques for Fast Predicate Abstraction -- The Power of Hybrid Acceleration -- Lookahead Widening -- Session 16. Tools Papers -- The Heuristic Theorem Prover: Yet Another SMT Modulo Theorem Prover -- LEVER: A Tool for Learning Based Verification -- Session 17. Memory Consistency -- Formal Verification of a Lazy Concurrent List-Based Set Algorithm -- Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study -- Fast and Generalized Polynomial Time Memory Consistency Verification -- Session 18. Shape Analysis -- Programs with Lists Are Counter Automata -- Lazy Shape Analysis -- Abstraction for Shape Analysis with Fast and Precise Transformers
- Control code
- 262693849
- Dimensions
- unknown
- Extent
- 1 online resource (xv, 564 pages)
- Form of item
- online
- Isbn
- 9783540374114
- Media category
- computer
- Media MARC source
- rdamedia
- Media type code
-
- c
- Other control number
- 10.1007/11817963
- Other physical details
- illustrations.
- http://library.link/vocab/ext/overdrive/overdriveId
- 978-3-540-37406-0
- Specific material designation
- remote
- System control number
- (OCoLC)262693849
- Label
- Computer aided verification : 18th international conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006 : proceedings, Thomas Ball, Robert B. Jones (eds.)
- Bibliography note
- Includes bibliographical references and index
- Carrier category
- online resource
- Carrier category code
-
- cr
- Carrier MARC source
- rdacarrier
- Color
- multicolored
- Content category
- text
- Content type code
-
- txt
- Content type MARC source
- rdacontent
- Contents
- Invited Talks -- Formal Specifications on Industrial-Strength Code--From Myth to Reality -- I Think I Voted: E-Voting vs. Democracy -- Playing with Verification, Planning and Aspects: Unusual Methods for Running Scenario-Based Programs -- The Ideal of Verified Software -- Session 1. Automata -- Antichains: A New Algorithm for Checking Universality of Finite Automata -- Safraless Compositional Synthesis -- Minimizing Generalized Büchi Automata -- Session 2. Tools Papers -- Ticc: A Tool for Interface Compatibility and Composition -- FAST Extended Release -- Session 3. Arithmetic -- Don't Care Words with an Application to the Automata-Based Approach for Real Addition -- A Fast Linear-Arithmetic Solver for DPLL(T) -- Session 4. SAT and Bounded Model Checking -- Bounded Model Checking for Weak Alternating Büchi Automata -- Deriving Small Unsatisfiable Cores with Dominators -- Session 5. Abstraction/Refinement -- Lazy Abstraction with Interpolants -- Using Statically Computed Invariants Inside the Predicate Abstraction and Refinement Loop -- Counterexamples with Loops for Predicate Abstraction -- Session 6. Tools Papers -- cascade: C Assertion Checker and Deductive Engine -- Yasm: A Software Model-Checker for Verification and Refutation -- Session 7. Symbolic Trajectory Evaluation -- SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation -- Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation -- Session 8. Property Specification and Verification -- Some Complexity Results for SystemVerilog Assertions -- Check It Out: On the Efficient Formal Verification of Live Sequence Charts -- Session 9. Time -- Symmetry Reduction for Probabilistic Model Checking -- Communicating Timed Automata: The More Synchronous, the More Difficult to Verify -- Allen Linear (Interval) Temporal Logic -- Translation to LTL and Monitor Synthesis -- Session 10. Tools Papers -- DiVinE -- A Tool for Distributed Verification -- EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation -- Session 11. Concurrency -- Symbolic Model Checking of Concurrent Programs Using Partial Orders and On-the-Fly Transactions -- Model Checking Multithreaded Programs with Asynchronous Atomic Methods -- Causal Atomicity -- Session 12. Trees, Pushdown Systems and Boolean Programs -- Languages of Nested Trees -- Improving Pushdown System Model Checking -- Repair of Boolean Programs with an Application to C -- Session 13. Termination -- Termination of Integer Linear Programs -- Automatic Termination Proofs for Programs with Shape-Shifting Heaps -- Termination Analysis with Calling Context Graphs -- Session 14. Tools Papers -- Terminator: Beyond Safety -- CUTE and jCUTE: Concolic Unit Testing and Explicit Path Model-Checking Tools -- Session 15. Abstract Interpretation -- SMT Techniques for Fast Predicate Abstraction -- The Power of Hybrid Acceleration -- Lookahead Widening -- Session 16. Tools Papers -- The Heuristic Theorem Prover: Yet Another SMT Modulo Theorem Prover -- LEVER: A Tool for Learning Based Verification -- Session 17. Memory Consistency -- Formal Verification of a Lazy Concurrent List-Based Set Algorithm -- Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study -- Fast and Generalized Polynomial Time Memory Consistency Verification -- Session 18. Shape Analysis -- Programs with Lists Are Counter Automata -- Lazy Shape Analysis -- Abstraction for Shape Analysis with Fast and Precise Transformers
- Control code
- 262693849
- Dimensions
- unknown
- Extent
- 1 online resource (xv, 564 pages)
- Form of item
- online
- Isbn
- 9783540374114
- Media category
- computer
- Media MARC source
- rdamedia
- Media type code
-
- c
- Other control number
- 10.1007/11817963
- Other physical details
- illustrations.
- http://library.link/vocab/ext/overdrive/overdriveId
- 978-3-540-37406-0
- Specific material designation
- remote
- System control number
- (OCoLC)262693849
Subject
- Computer software -- Verification
- Computer software -- Verification
- Computer software -- Verification
- Computer software -- Verification -- Congresses
- Conference papers and proceedings
- Conference papers and proceedings
- Informatique
- Integrated circuits -- Verification
- Integrated circuits -- Verification
- Integrated circuits -- Verification
- Integrated circuits -- Verification -- Congresses
- Logiciels -- Vérification
- Circuits intégrés -- Vérification
Genre
Member of
- LNCS sublibrary, SL 1, Theoretical computer science and general issues
- Lecture notes in computer science, 4144
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