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The Resource Correct hardware design and verification methods : 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 : proceedings, Dominique Borrione, Wolfgang Paul (eds.)

Correct hardware design and verification methods : 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 : proceedings, Dominique Borrione, Wolfgang Paul (eds.)

Work
Publication
Extent
1 online resource (xii, 412 pages)
Contents
  • Invited Talks
  • Is Formal Verification Bound to Remain a Junior Partner of Simulation?
  • Verification Challenges in Configurable Processor Design with ASIP Meister
  • Tutorial
  • Towards the Pervasive Verification of Automotive Systems
  • Functional Approaches to Design Description
  • Wired: Wire-Aware Circuit Design
  • Formalization of the DE2 Language
  • Game Solving Approaches
  • Finding and Fixing Faults
  • Verifying Quantitative Properties Using Bound Functions
  • Abstraction
  • How Thorough Is Thorough Enough?
  • Interleaved Invariant Checking with Dynamic Abstraction
  • Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units
  • Algorithms and Techniques for Speeding (DD-Based) Verification 1
  • Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting
  • Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation
  • Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning
  • Real Time and LTL Model Checking
  • Real-Time Model Checking Is Really Simple
  • Temporal Modalities for Concisely Capturing Timing Diagrams
  • Regular Vacuity
  • Algorithms and Techniques for Speeding Verification 2
  • Automatic Generation of Hints for Symbolic Traversal
  • Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies
  • A New SAT-Based Algorithm for Symbolic Trajectory Evaluation
  • Evaluation of SAT-Based Tools
  • An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment
  • Model Reduction
  • Exploiting Constraints in Transformation-Based Verification
  • Identification and Counter Abstraction for Full Virtual Symmetry
  • Verification of Memory Hierarchy Mechanisms
  • On the Verification of Memory Management Mechanisms
  • Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification
  • Short Papers
  • Symbolic Partial Order Reduction for Rule Based Transition Systems
  • Verifying Timing Behavior by Abstract Interpretation of Executable Code
  • Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths
  • Deadlock Prevention in the Æthereal Protocol
  • Acceleration of SAT-Based Iterative Property Checking
  • Error Detection Using BMC in a Parallel Environment
  • Formal Verification of Synchronizers
  • A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems
  • Improvements to the Implementation of Interpolant-Based Model Checking
  • High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
  • Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic
  • Resolving Quartz Overloading
  • FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers
  • Predictive Reachability Using a Sample-Based Approach
  • Minimizing Counterexample of ACTL Property
  • Data Refinement for Synchronous System Specification and Construction
  • Introducing Abstractions via Rewriting
  • A Case Study: Formal Verification of Processor Critical Properties
Isbn
9781281391346
Instance
Label
Correct hardware design and verification methods : 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 : proceedings
Title
Correct hardware design and verification methods
Title remainder
13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 : proceedings
Statement of responsibility
Dominique Borrione, Wolfgang Paul (eds.)
Title variation
  • CHARME 2005
  • IFIP CHARME 2005
Creator
Contributor
Subject
Genre
Language
eng
Member of
Cataloging source
GW5XE
Dewey number
621.39/5
Illustrations
illustrations
Index
index present
LC call number
TK7874.75
LC item number
.C453 2005eb
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2005
http://bibfra.me/vocab/lite/meetingName
CHARME 2005
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorDate
1951-
http://library.link/vocab/relatedWorkOrContributorName
  • Borrione, Dominique
  • Paul, Wolfgang J.
Series statement
Lecture notes in computer science,
Series volume
3725
http://library.link/vocab/subjectName
  • Integrated circuits
  • Integrated circuits
  • TECHNOLOGY & ENGINEERING
  • TECHNOLOGY & ENGINEERING
  • COMPUTERS
  • Informatique
  • Integrated circuits
  • Integrated circuits
  • Circuit intégré à très grande échelle
  • Conception assistée par ordinateur
  • Circuit intégré
  • Vérification formelle
  • Essai technique
  • Model-checking (Informatique)
Label
Correct hardware design and verification methods : 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 : proceedings, Dominique Borrione, Wolfgang Paul (eds.)
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Invited Talks -- Is Formal Verification Bound to Remain a Junior Partner of Simulation? -- Verification Challenges in Configurable Processor Design with ASIP Meister -- Tutorial -- Towards the Pervasive Verification of Automotive Systems -- Functional Approaches to Design Description -- Wired: Wire-Aware Circuit Design -- Formalization of the DE2 Language -- Game Solving Approaches -- Finding and Fixing Faults -- Verifying Quantitative Properties Using Bound Functions -- Abstraction -- How Thorough Is Thorough Enough? -- Interleaved Invariant Checking with Dynamic Abstraction -- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units -- Algorithms and Techniques for Speeding (DD-Based) Verification 1 -- Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting -- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation -- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning -- Real Time and LTL Model Checking -- Real-Time Model Checking Is Really Simple -- Temporal Modalities for Concisely Capturing Timing Diagrams -- Regular Vacuity -- Algorithms and Techniques for Speeding Verification 2 -- Automatic Generation of Hints for Symbolic Traversal -- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies -- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation -- Evaluation of SAT-Based Tools -- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment -- Model Reduction -- Exploiting Constraints in Transformation-Based Verification -- Identification and Counter Abstraction for Full Virtual Symmetry -- Verification of Memory Hierarchy Mechanisms -- On the Verification of Memory Management Mechanisms -- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification -- Short Papers -- Symbolic Partial Order Reduction for Rule Based Transition Systems -- Verifying Timing Behavior by Abstract Interpretation of Executable Code -- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths -- Deadlock Prevention in the Æthereal Protocol -- Acceleration of SAT-Based Iterative Property Checking -- Error Detection Using BMC in a Parallel Environment -- Formal Verification of Synchronizers -- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems -- Improvements to the Implementation of Interpolant-Based Model Checking -- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design -- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic -- Resolving Quartz Overloading -- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers -- Predictive Reachability Using a Sample-Based Approach -- Minimizing Counterexample of ACTL Property -- Data Refinement for Synchronous System Specification and Construction -- Introducing Abstractions via Rewriting -- A Case Study: Formal Verification of Processor Critical Properties
Control code
262681856
Dimensions
unknown
Extent
1 online resource (xii, 412 pages)
Form of item
online
Isbn
9781281391346
Lccn
2005932937
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
  • 10.1007/11560548
  • 9783540291053
Other physical details
illustrations.
http://library.link/vocab/ext/overdrive/overdriveId
978-3-540-29105-3
Publisher number
11560548
Specific material designation
remote
System control number
(OCoLC)262681856
Label
Correct hardware design and verification methods : 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 : proceedings, Dominique Borrione, Wolfgang Paul (eds.)
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Invited Talks -- Is Formal Verification Bound to Remain a Junior Partner of Simulation? -- Verification Challenges in Configurable Processor Design with ASIP Meister -- Tutorial -- Towards the Pervasive Verification of Automotive Systems -- Functional Approaches to Design Description -- Wired: Wire-Aware Circuit Design -- Formalization of the DE2 Language -- Game Solving Approaches -- Finding and Fixing Faults -- Verifying Quantitative Properties Using Bound Functions -- Abstraction -- How Thorough Is Thorough Enough? -- Interleaved Invariant Checking with Dynamic Abstraction -- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units -- Algorithms and Techniques for Speeding (DD-Based) Verification 1 -- Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting -- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation -- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning -- Real Time and LTL Model Checking -- Real-Time Model Checking Is Really Simple -- Temporal Modalities for Concisely Capturing Timing Diagrams -- Regular Vacuity -- Algorithms and Techniques for Speeding Verification 2 -- Automatic Generation of Hints for Symbolic Traversal -- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies -- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation -- Evaluation of SAT-Based Tools -- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment -- Model Reduction -- Exploiting Constraints in Transformation-Based Verification -- Identification and Counter Abstraction for Full Virtual Symmetry -- Verification of Memory Hierarchy Mechanisms -- On the Verification of Memory Management Mechanisms -- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification -- Short Papers -- Symbolic Partial Order Reduction for Rule Based Transition Systems -- Verifying Timing Behavior by Abstract Interpretation of Executable Code -- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths -- Deadlock Prevention in the Æthereal Protocol -- Acceleration of SAT-Based Iterative Property Checking -- Error Detection Using BMC in a Parallel Environment -- Formal Verification of Synchronizers -- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems -- Improvements to the Implementation of Interpolant-Based Model Checking -- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design -- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic -- Resolving Quartz Overloading -- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers -- Predictive Reachability Using a Sample-Based Approach -- Minimizing Counterexample of ACTL Property -- Data Refinement for Synchronous System Specification and Construction -- Introducing Abstractions via Rewriting -- A Case Study: Formal Verification of Processor Critical Properties
Control code
262681856
Dimensions
unknown
Extent
1 online resource (xii, 412 pages)
Form of item
online
Isbn
9781281391346
Lccn
2005932937
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
  • 10.1007/11560548
  • 9783540291053
Other physical details
illustrations.
http://library.link/vocab/ext/overdrive/overdriveId
978-3-540-29105-3
Publisher number
11560548
Specific material designation
remote
System control number
(OCoLC)262681856

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