Coverart for item
The Resource Correct hardware design and verification methods : IFIP WG10.5 advanced research working conference, CHARME ̕95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking(eds.)

Correct hardware design and verification methods : IFIP WG10.5 advanced research working conference, CHARME ̕95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking(eds.)

Label
Correct hardware design and verification methods : IFIP WG10.5 advanced research working conference, CHARME ̕95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings
Title
Correct hardware design and verification methods
Title remainder
IFIP WG10.5 advanced research working conference, CHARME ̕95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings
Statement of responsibility
Paolo E. Camurati, Hans Eveking(eds.)
Title variation
CHARME '95
Creator
Contributor
Subject
Genre
Language
eng
Summary
"This book constitutes the refereed proceedings of the IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design Methodologies, CHARME '95, held in Frankfurt, Germany, in October 1995. The 20 revised full papers presented were carefully selected by the program committee and address all current aspects of research and advanced applications in the field of formal verification of hardware. Among the topics covered are model checking, theorem proving, formally verified synthesis, process algebras, finite state systems, verification environments, language containment, and VHDL."--PUBLISHER'S WEBSITE
Member of
Cataloging source
DLC
Illustrations
illustrations
Index
no index present
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
1995
http://bibfra.me/vocab/lite/meetingName
Advanced Research Working Conference on Correct Hardware Design Methodologies
Nature of contents
bibliography
http://library.link/vocab/relatedWorkOrContributorName
  • Camurati, Paolo
  • Eveking, Hans
Series statement
Lecture notes in computer science
Series volume
987
http://library.link/vocab/subjectName
  • Integrated circuits
  • Integrated circuits
  • Integrated circuits
  • Computer-aided design
Label
Correct hardware design and verification methods : IFIP WG10.5 advanced research working conference, CHARME ̕95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking(eds.)
Instantiates
Publication
Bibliography note
Includes bibliographical references
Carrier category
volume
Carrier category code
  • nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
What if model checking must be truly symbolic / H. Hungar ... [et al.] -- Automatic verification of the SCI cache coherence protocol / U. stern, D.L. Dill -- Describing and verifying synchronous circuits with the Boyer-Moore theorem prover / L. Pierre -- Problems encountered in the machine-assisted proof of hardware / P. Curzon -- Formally embedding existing high level synthesis algorithms / D. Eisenbiegler, R. Kumar -- Formal design of a class of computers / L.G. Wang, M. Mendler -- Symbolic analysis and verification of CPA descriptions / M.C. McFarland, T.J. Kowalski -- A foundation for formal reuse of hardware / A.C.V. de Melo, H. Barringer -- State enumeration with abstract descriptions of state machines / F. Corella ... [et al.] -- Transforming boolean relations by symbolic encoding / G. Cabodi ... [et al.] -- Design error diagnosis in sequential circuits / A. Wahba, D. Borrione -- Timing analysis of asynchronous circuits using timed automata / O. Maler, A. Pnueli -- Improved probabilistic verification by hash compaction / U. Stern, D.L. Dill -- Formal support for the ELLA hardware description language / H. Barringer, B. Monahan, A. Williams -- Verifying hardware components within JACK / R. De Nicola ... [et al.] -- Language containment of non-deterministic [omega]-automata / S. Taşiran, R. Hojati, R.K. Brayton -- A partial-order approach to the verification of concurrent systems : checking liveness properties / D. Bolignano -- Semantics of a verification-oriented subset of VHDL / D. Déharbe, D. Borrione -- Reasoning about VHDL using operational and observational semantics / K.G.W. Gossens -- A symbolic relation for a subset of VHDL '87 descriptions and its application to symbolic model checking / E. Encrenaz
Control code
33103673
Dimensions
24 cm
Extent
viii, 342 pages
Isbn
9783540603856
Isbn Type
(acid-free paper)
Lccn
95039591
Media category
unmediated
Media MARC source
rdamedia
Media type code
  • n
Other physical details
illustrations
System control number
(WaOLN)1682906
Label
Correct hardware design and verification methods : IFIP WG10.5 advanced research working conference, CHARME ̕95, Frankfurt/Main, Germany, October 2-4, 1995 : proceedings, Paolo E. Camurati, Hans Eveking(eds.)
Publication
Bibliography note
Includes bibliographical references
Carrier category
volume
Carrier category code
  • nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
What if model checking must be truly symbolic / H. Hungar ... [et al.] -- Automatic verification of the SCI cache coherence protocol / U. stern, D.L. Dill -- Describing and verifying synchronous circuits with the Boyer-Moore theorem prover / L. Pierre -- Problems encountered in the machine-assisted proof of hardware / P. Curzon -- Formally embedding existing high level synthesis algorithms / D. Eisenbiegler, R. Kumar -- Formal design of a class of computers / L.G. Wang, M. Mendler -- Symbolic analysis and verification of CPA descriptions / M.C. McFarland, T.J. Kowalski -- A foundation for formal reuse of hardware / A.C.V. de Melo, H. Barringer -- State enumeration with abstract descriptions of state machines / F. Corella ... [et al.] -- Transforming boolean relations by symbolic encoding / G. Cabodi ... [et al.] -- Design error diagnosis in sequential circuits / A. Wahba, D. Borrione -- Timing analysis of asynchronous circuits using timed automata / O. Maler, A. Pnueli -- Improved probabilistic verification by hash compaction / U. Stern, D.L. Dill -- Formal support for the ELLA hardware description language / H. Barringer, B. Monahan, A. Williams -- Verifying hardware components within JACK / R. De Nicola ... [et al.] -- Language containment of non-deterministic [omega]-automata / S. Taşiran, R. Hojati, R.K. Brayton -- A partial-order approach to the verification of concurrent systems : checking liveness properties / D. Bolignano -- Semantics of a verification-oriented subset of VHDL / D. Déharbe, D. Borrione -- Reasoning about VHDL using operational and observational semantics / K.G.W. Gossens -- A symbolic relation for a subset of VHDL '87 descriptions and its application to symbolic model checking / E. Encrenaz
Control code
33103673
Dimensions
24 cm
Extent
viii, 342 pages
Isbn
9783540603856
Isbn Type
(acid-free paper)
Lccn
95039591
Media category
unmediated
Media MARC source
rdamedia
Media type code
  • n
Other physical details
illustrations
System control number
(WaOLN)1682906

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