Coverart for item
The Resource Euro-DAC '96, European Design Automation Conference with Euro-VHDL '96 and Exhibition : proceedings, Geneva, Switzerland, September 16-20, 1996, sponsored by Gesellschaft für Informatik e.V. [and others]

Euro-DAC '96, European Design Automation Conference with Euro-VHDL '96 and Exhibition : proceedings, Geneva, Switzerland, September 16-20, 1996, sponsored by Gesellschaft für Informatik e.V. [and others]

Label
Euro-DAC '96, European Design Automation Conference with Euro-VHDL '96 and Exhibition : proceedings, Geneva, Switzerland, September 16-20, 1996
Title
Euro-DAC '96, European Design Automation Conference with Euro-VHDL '96 and Exhibition
Title remainder
proceedings, Geneva, Switzerland, September 16-20, 1996
Statement of responsibility
sponsored by Gesellschaft für Informatik e.V. [and others]
Title variation
  • European Design Automation Conference with Euro-VHDL '96 and Exhibition
  • Euro-VHDL '96
  • Proceedings of the Conference with EURO-VHDL '96 and Exhibition on European Design Automation
Creator
Contributor
Subject
Genre
Language
eng
Related
Member of
Cataloging source
OCL
Dewey number
621.3815
Illustrations
illustrations
Index
index present
LC call number
TK7874
LC item number
.E788 1996
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
1996
http://bibfra.me/vocab/lite/meetingName
European Design Automation Conference
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
Gesellschaft für Informatik
http://library.link/vocab/subjectName
  • Integrated circuits
  • Electronic circuit design
  • VHDL (Computer hardware description language)
  • Electronic circuit design
  • Integrated circuits
  • VHDL (Computer hardware description language)
Label
Euro-DAC '96, European Design Automation Conference with Euro-VHDL '96 and Exhibition : proceedings, Geneva, Switzerland, September 16-20, 1996, sponsored by Gesellschaft für Informatik e.V. [and others]
Instantiates
Publication
Note
  • "IEEE order plan catalog number 96CB36000"--Title page verso
  • "IEEE Computer Society Press order number PR07573"--Title page verso
  • "ACM order number 478962"--Title page verso
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Session D-01: Analog and mixed mode simulation -- Session D-02: Low power synthesis -- Session D-03: Design experience -- Session D-04: Timing modeling -- Session D-05: Design flow and design management -- Session D-06: (Panel) What's hot in low power design? -- Session D-07: Partitioning -- Session D-08: Logic and FSM synthesis -- Session D-09: BDD optimization techniques -- Session D-10: Codesign methodology and cospecification -- Session D-11: System level design and synthesis -- Session D-12: New aspects on testing -- Session D-13: Codesign methodology and cosimulation -- Session D-14: (Joint Panel EURO-DAC and EURO-VHDL) Which formal verification technique is more applicable in industry today: equivalence checking or property checking? -- Session D-15: Key technologies and CAD of microsystems -- Session D-16: Asynchronous synthesis and storage optimization -- Session D-17: Modelling, simulation of microsystems and multi layer routing in PCBs -- Session D-18: Timing issues in synthesis -- Session D-19: Physical design for deep submicron -- Session D-20: Architectural synthesis techniques -- Session D-21: (Panel) When do EDA tools hit the submicron wall? -- Session D-22: CAD for analog circuit -- Session V-01: Analysis tools -- Session V-02: Beyond VHDL -- Session V-03: (Panel) What advantages can we expect from object-oriented extensions to VHDL? -- Session V-04: Fault modeling and design for testability -- Session V-05: Formal methods -- Session V-06: Modeling methodologies -- Session V-07: Synthesis -- Session V-08: System level design -- Session V-09: VHDL and mixed signal design -- Session V-10: (Panel) The open forum model
Control code
47882476
Dimensions
unknown
Extent
1 online resource (xxiii, 579 pages)
Form of item
online
Isbn
9780818675737
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations
Sound
unknown sound
Specific material designation
remote
System control number
(OCoLC)47882476
Label
Euro-DAC '96, European Design Automation Conference with Euro-VHDL '96 and Exhibition : proceedings, Geneva, Switzerland, September 16-20, 1996, sponsored by Gesellschaft für Informatik e.V. [and others]
Publication
Note
  • "IEEE order plan catalog number 96CB36000"--Title page verso
  • "IEEE Computer Society Press order number PR07573"--Title page verso
  • "ACM order number 478962"--Title page verso
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Session D-01: Analog and mixed mode simulation -- Session D-02: Low power synthesis -- Session D-03: Design experience -- Session D-04: Timing modeling -- Session D-05: Design flow and design management -- Session D-06: (Panel) What's hot in low power design? -- Session D-07: Partitioning -- Session D-08: Logic and FSM synthesis -- Session D-09: BDD optimization techniques -- Session D-10: Codesign methodology and cospecification -- Session D-11: System level design and synthesis -- Session D-12: New aspects on testing -- Session D-13: Codesign methodology and cosimulation -- Session D-14: (Joint Panel EURO-DAC and EURO-VHDL) Which formal verification technique is more applicable in industry today: equivalence checking or property checking? -- Session D-15: Key technologies and CAD of microsystems -- Session D-16: Asynchronous synthesis and storage optimization -- Session D-17: Modelling, simulation of microsystems and multi layer routing in PCBs -- Session D-18: Timing issues in synthesis -- Session D-19: Physical design for deep submicron -- Session D-20: Architectural synthesis techniques -- Session D-21: (Panel) When do EDA tools hit the submicron wall? -- Session D-22: CAD for analog circuit -- Session V-01: Analysis tools -- Session V-02: Beyond VHDL -- Session V-03: (Panel) What advantages can we expect from object-oriented extensions to VHDL? -- Session V-04: Fault modeling and design for testability -- Session V-05: Formal methods -- Session V-06: Modeling methodologies -- Session V-07: Synthesis -- Session V-08: System level design -- Session V-09: VHDL and mixed signal design -- Session V-10: (Panel) The open forum model
Control code
47882476
Dimensions
unknown
Extent
1 online resource (xxiii, 579 pages)
Form of item
online
Isbn
9780818675737
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations
Sound
unknown sound
Specific material designation
remote
System control number
(OCoLC)47882476

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