Coverart for item
The Resource Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds

Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds

Label
Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings
Title
Formal methods in computer-aided design
Title remainder
third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings
Statement of responsibility
Warren A. Hunt, Jr., Steven D. Johnson, eds
Creator
Contributor
Subject
Genre
Language
eng
Summary
This book constitutes the refereed proceedings of the Third International Conference on Formal Methods in Computer-Aided Design, FMCAD 2000, held in Austin, Texas in November 2000. The 30 revised full papers presented together with two invited contributions were carefully reviewed and selected from 63 submissions. All current issues of research and development approaches based on formal methods for the design and analysis of systems are addressed. Among the topics covered are formal verification, formal specification, systems analysis, program analysis, model checking, automated modeling, program semantics, theorem proving, symbolic simulation, and transition systems
Member of
Cataloging source
COO
Dewey number
621.39/2
Illustrations
illustrations
Index
index present
LC call number
TK7885.A1
LC item number
F59 2000
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2000
http://bibfra.me/vocab/lite/meetingName
FMCAD 2000
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorDate
1958-
http://library.link/vocab/relatedWorkOrContributorName
  • Hunt, Warren A.
  • Johnson, Steven D.
Series statement
Lecture notes in computer science
Series volume
1954
http://library.link/vocab/subjectName
  • Computer engineering
  • Integrated circuits
  • Computer engineering
  • Integrated circuits
Label
Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Applications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables
Control code
619611810
Dimensions
unknown
Extent
1 online resource (xi, 537 pages)
Form of item
online
Isbn
9783540409229
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
10.1007/3-540-40922-X
Other physical details
illustrations.
Specific material designation
remote
System control number
(OCoLC)619611810
Label
Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Applications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables
Control code
619611810
Dimensions
unknown
Extent
1 online resource (xi, 537 pages)
Form of item
online
Isbn
9783540409229
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other control number
10.1007/3-540-40922-X
Other physical details
illustrations.
Specific material designation
remote
System control number
(OCoLC)619611810

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