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The Resource Modeling and simulation for RF system design, by Ronny Frevert [and others]

Modeling and simulation for RF system design, by Ronny Frevert [and others]

Label
Modeling and simulation for RF system design
Title
Modeling and simulation for RF system design
Statement of responsibility
by Ronny Frevert [and others]
Title variation
Modeling and simulation for radio frequency system design
Contributor
Subject
Language
eng
Cataloging source
OHX
Illustrations
illustrations
Index
index present
Literary form
non fiction
Nature of contents
  • theses
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
Frevert, Ronny
http://library.link/vocab/subjectName
  • Telecommunication systems
  • Telecommunication systems
  • VHDL (Computer hardware description language)
Label
Modeling and simulation for RF system design, by Ronny Frevert [and others]
Instantiates
Publication
Note
CD-ROM includes: models, test-benches, scripts, and documents
Accompanying material
1 CD-ROM (4 3/4 in.)
Bibliography note
Includes bibliographical references (pages 285-286) and index
Carrier category
computer disc
Carrier category code
cd
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • 9
  • 66
  • 6.3.1
  • Network analysis problem
  • 67
  • 6.3.2
  • Nature, terminal and branch quantity declarations
  • 71
  • 6.3.3
  • Simultaneous statements and free quantity declarations
  • 78
  • 2.3
  • 6.3.4
  • Example of a conservative system -- A-law companding
  • 85
  • 6.3.5
  • Attributes in VHDL-AMS
  • 88
  • 6.3.6
  • Example -- higher order lowpass filter
  • 103
  • 6.4
  • Bottom-up Verification
  • Description of Nonconservative Systems
  • 105
  • 6.5
  • Mixed-Signal Simulation
  • 107
  • 6.5.1
  • Attributes for mixed-signal modeling
  • 108
  • 6.5.2
  • Mixed-signal simulation cycle
  • 11
  • 114
  • 6.6
  • Analysis Domains
  • 116
  • 6.6.1
  • Supported domains
  • 116
  • 6.6.2
  • Small-signal and noise domain simulation
  • 118
  • 3
  • 7
  • Selected RF Blocks in VHDL-AMS
  • 127
  • 7.1
  • Library Overview
  • 127
  • 7.2
  • Signal Sources
  • 128
  • 7.2.1
  • Simulation Tools in System Design
  • Independent sources
  • 128
  • 7.2.2
  • Modulated sources
  • 130
  • 7.2.3
  • Wobble generator
  • 133
  • 7.2.4
  • Pseudorandom binary source
  • 15
  • 135
  • 7.3
  • Basic RF Building Blocks
  • 137
  • 7.3.1
  • Low-noise amplifier
  • 137
  • 7.3.2
  • Mixer
  • 142
  • 3.1
  • 7.3.3
  • Charge pump
  • 146
  • 7.3.4
  • Analog VCO
  • 150
  • 7.3.5
  • Digital VCO
  • 153
  • 7.3.6
  • Use of Simulation Tools within the Design Flow
  • Filters
  • 157
  • 7.3.7
  • Switch
  • 163
  • 7.3.8
  • General n-bit A/D and D/A converter
  • 164
  • 7.3.9
  • Simple channel
  • 15
  • 169
  • 7.4
  • Measurement and Observation Units
  • 174
  • 7.4.1
  • Peak detector
  • 174
  • 7.4.2
  • Frequency measurement unit
  • 175
  • 2
  • 3.2
  • 7.4.3
  • Power meter
  • 178
  • 7.5
  • Block Level Example of a Linear PLL
  • 183
  • 8
  • Macromodeling in VHDL-AMS
  • 191
  • 8.2
  • Specific Simulation Algorithms of RF Simulators
  • General Methodology
  • 191
  • 8.3
  • Input and Output Stages
  • 194
  • 8.3.1
  • Input stages
  • 194
  • 8.3.2
  • Output stages
  • 17
  • 197
  • 8.4
  • OpAmp Macromodel
  • 199
  • 9
  • Complex Example: Wlan Receiver
  • 203
  • 9.2
  • Example Specification
  • 204
  • 3.3
  • 9.3
  • Example Modeling
  • 207
  • 9.4
  • Example Calibration
  • 211
  • 9.5
  • Example Verification
  • 214
  • 10
  • Criteria of the Simulator Selection
  • Modeling of Analog Blocks in Verilog-A
  • 219
  • 10.2
  • Writing Custom Behavioral Models
  • 220
  • 10.2.1
  • Verilog-A principles
  • 220
  • 10.2.2
  • LNA modeling example
  • 21
  • 222
  • 10.2.3
  • Creating a Verilog-A model
  • 226
  • 10.3
  • Overview of the Cadence Model Library rfLib
  • 231
  • 10.4
  • Modeling and Simulation of a WLAN Receiver
  • 236
  • 3.4
  • 10.4.1
  • WLAN receiver modeling using Cadence libraries
  • 237
  • 10.4.2
  • Simulation of the WLAN receiver
  • 240
  • 11
  • Characterization for Bottom-Up Verification
  • 247
  • 11.1
  • Internet Resources for Simulation Tools
  • Concept of Characterization
  • 247
  • 11.2
  • RF Characteristics and Parameters
  • 248
  • 11.3
  • Application of Characterization
  • 252
  • 11.4
  • Example Characterization of an LNA
  • 23
  • 254
  • 11.5
  • Characterization Environment
  • 258
  • 11.6
  • Characterization Using the OCEAN Script Language
  • 262
  • 11.6.1
  • Creation of the testbench schematic
  • 262
  • 4
  • 11.6.2
  • Analysis settings and simulation
  • 263
  • 11.6.3
  • Combination and extension of the OCEAN scripts
  • 266
  • 12
  • Advanced Methods for Overall System Specification and Validation
  • 271
  • 12.1
  • Design Flow Overview
  • System Level Modeling
  • Gap between System Level and Block Level Simulation
  • 271
  • 12.2
  • File Coupling of Simulators
  • 272
  • 12.3
  • Direct Cosimulation of System Level and Analog Simulators
  • 273
  • 12.4
  • Generated Black Box Models
  • 25
  • 279
  • 4.1
  • System Level Simulation
  • 25
  • 4.2
  • Simulation Technology of System Level Simulators
  • 26
  • 4.3
  • Complex Baseband Simulation
  • 7
  • 27
  • 4.3.1
  • Principle
  • 27
  • 4.3.2
  • Example for baseband simulation
  • 30
  • 4.3.3
  • Restrictions and advantages of baseband modeling
  • 30
  • 2.1
  • 4.4
  • Model Libraries for System Simulation
  • 31
  • 4.5
  • Creation of Own Primitive and Hierarchical Models
  • 33
  • 4.5.1
  • SPW modeling example
  • 33
  • 5
  • Design Levels
  • VHDL-AMS for Block Level Simulation
  • 39
  • 5.2
  • VHDL-AMS Standardization
  • 40
  • 5.3
  • A Simple Block Level Example -- Analog PLL
  • 41
  • 5.3.1
  • Mathematical models of basic blocks
  • 7
  • 42
  • 5.3.2
  • Structural description of the PLL circuit in VHDL-AMS
  • 44
  • 5.3.3
  • VHDL-AMS description of basic blocks
  • 47
  • 6
  • Introduction to VHDL-AMS
  • 51
  • 2.2
  • 6.1
  • Aim of this Introduction
  • 51
  • 6.2
  • Repetition of Basics of VHDL 1076-1993
  • 52
  • 6.2.1
  • Design units
  • 52
  • 6.2.2
  • Top-down System Design
  • Logical libraries and compilation of design units
  • 56
  • 6.2.3
  • Concurrent statements
  • 60
  • 6.2.4
  • A simple pure digital example -- divider
  • 65
  • 6.3
  • Conservative Systems Description
Control code
62363726
Dimensions
25 cm +
Dimensions
4 3/4 in. or 12 cm.
Extent
viii, 291 pages
File format
multiple file formats
Isbn
9780387275857
Isbn Type
(e-book)
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
  • 9780387275840 (HB)
  • 9780387275857 (e-book)
Other physical details
illustrations
Specific material designation
optical disk
System details
System requirements for disc: IBM PC or compatible; Windows; CD-ROM drive, Internet browser
Label
Modeling and simulation for RF system design, by Ronny Frevert [and others]
Publication
Note
CD-ROM includes: models, test-benches, scripts, and documents
Accompanying material
1 CD-ROM (4 3/4 in.)
Bibliography note
Includes bibliographical references (pages 285-286) and index
Carrier category
computer disc
Carrier category code
cd
Carrier MARC source
rdacarrier
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
  • 9
  • 66
  • 6.3.1
  • Network analysis problem
  • 67
  • 6.3.2
  • Nature, terminal and branch quantity declarations
  • 71
  • 6.3.3
  • Simultaneous statements and free quantity declarations
  • 78
  • 2.3
  • 6.3.4
  • Example of a conservative system -- A-law companding
  • 85
  • 6.3.5
  • Attributes in VHDL-AMS
  • 88
  • 6.3.6
  • Example -- higher order lowpass filter
  • 103
  • 6.4
  • Bottom-up Verification
  • Description of Nonconservative Systems
  • 105
  • 6.5
  • Mixed-Signal Simulation
  • 107
  • 6.5.1
  • Attributes for mixed-signal modeling
  • 108
  • 6.5.2
  • Mixed-signal simulation cycle
  • 11
  • 114
  • 6.6
  • Analysis Domains
  • 116
  • 6.6.1
  • Supported domains
  • 116
  • 6.6.2
  • Small-signal and noise domain simulation
  • 118
  • 3
  • 7
  • Selected RF Blocks in VHDL-AMS
  • 127
  • 7.1
  • Library Overview
  • 127
  • 7.2
  • Signal Sources
  • 128
  • 7.2.1
  • Simulation Tools in System Design
  • Independent sources
  • 128
  • 7.2.2
  • Modulated sources
  • 130
  • 7.2.3
  • Wobble generator
  • 133
  • 7.2.4
  • Pseudorandom binary source
  • 15
  • 135
  • 7.3
  • Basic RF Building Blocks
  • 137
  • 7.3.1
  • Low-noise amplifier
  • 137
  • 7.3.2
  • Mixer
  • 142
  • 3.1
  • 7.3.3
  • Charge pump
  • 146
  • 7.3.4
  • Analog VCO
  • 150
  • 7.3.5
  • Digital VCO
  • 153
  • 7.3.6
  • Use of Simulation Tools within the Design Flow
  • Filters
  • 157
  • 7.3.7
  • Switch
  • 163
  • 7.3.8
  • General n-bit A/D and D/A converter
  • 164
  • 7.3.9
  • Simple channel
  • 15
  • 169
  • 7.4
  • Measurement and Observation Units
  • 174
  • 7.4.1
  • Peak detector
  • 174
  • 7.4.2
  • Frequency measurement unit
  • 175
  • 2
  • 3.2
  • 7.4.3
  • Power meter
  • 178
  • 7.5
  • Block Level Example of a Linear PLL
  • 183
  • 8
  • Macromodeling in VHDL-AMS
  • 191
  • 8.2
  • Specific Simulation Algorithms of RF Simulators
  • General Methodology
  • 191
  • 8.3
  • Input and Output Stages
  • 194
  • 8.3.1
  • Input stages
  • 194
  • 8.3.2
  • Output stages
  • 17
  • 197
  • 8.4
  • OpAmp Macromodel
  • 199
  • 9
  • Complex Example: Wlan Receiver
  • 203
  • 9.2
  • Example Specification
  • 204
  • 3.3
  • 9.3
  • Example Modeling
  • 207
  • 9.4
  • Example Calibration
  • 211
  • 9.5
  • Example Verification
  • 214
  • 10
  • Criteria of the Simulator Selection
  • Modeling of Analog Blocks in Verilog-A
  • 219
  • 10.2
  • Writing Custom Behavioral Models
  • 220
  • 10.2.1
  • Verilog-A principles
  • 220
  • 10.2.2
  • LNA modeling example
  • 21
  • 222
  • 10.2.3
  • Creating a Verilog-A model
  • 226
  • 10.3
  • Overview of the Cadence Model Library rfLib
  • 231
  • 10.4
  • Modeling and Simulation of a WLAN Receiver
  • 236
  • 3.4
  • 10.4.1
  • WLAN receiver modeling using Cadence libraries
  • 237
  • 10.4.2
  • Simulation of the WLAN receiver
  • 240
  • 11
  • Characterization for Bottom-Up Verification
  • 247
  • 11.1
  • Internet Resources for Simulation Tools
  • Concept of Characterization
  • 247
  • 11.2
  • RF Characteristics and Parameters
  • 248
  • 11.3
  • Application of Characterization
  • 252
  • 11.4
  • Example Characterization of an LNA
  • 23
  • 254
  • 11.5
  • Characterization Environment
  • 258
  • 11.6
  • Characterization Using the OCEAN Script Language
  • 262
  • 11.6.1
  • Creation of the testbench schematic
  • 262
  • 4
  • 11.6.2
  • Analysis settings and simulation
  • 263
  • 11.6.3
  • Combination and extension of the OCEAN scripts
  • 266
  • 12
  • Advanced Methods for Overall System Specification and Validation
  • 271
  • 12.1
  • Design Flow Overview
  • System Level Modeling
  • Gap between System Level and Block Level Simulation
  • 271
  • 12.2
  • File Coupling of Simulators
  • 272
  • 12.3
  • Direct Cosimulation of System Level and Analog Simulators
  • 273
  • 12.4
  • Generated Black Box Models
  • 25
  • 279
  • 4.1
  • System Level Simulation
  • 25
  • 4.2
  • Simulation Technology of System Level Simulators
  • 26
  • 4.3
  • Complex Baseband Simulation
  • 7
  • 27
  • 4.3.1
  • Principle
  • 27
  • 4.3.2
  • Example for baseband simulation
  • 30
  • 4.3.3
  • Restrictions and advantages of baseband modeling
  • 30
  • 2.1
  • 4.4
  • Model Libraries for System Simulation
  • 31
  • 4.5
  • Creation of Own Primitive and Hierarchical Models
  • 33
  • 4.5.1
  • SPW modeling example
  • 33
  • 5
  • Design Levels
  • VHDL-AMS for Block Level Simulation
  • 39
  • 5.2
  • VHDL-AMS Standardization
  • 40
  • 5.3
  • A Simple Block Level Example -- Analog PLL
  • 41
  • 5.3.1
  • Mathematical models of basic blocks
  • 7
  • 42
  • 5.3.2
  • Structural description of the PLL circuit in VHDL-AMS
  • 44
  • 5.3.3
  • VHDL-AMS description of basic blocks
  • 47
  • 6
  • Introduction to VHDL-AMS
  • 51
  • 2.2
  • 6.1
  • Aim of this Introduction
  • 51
  • 6.2
  • Repetition of Basics of VHDL 1076-1993
  • 52
  • 6.2.1
  • Design units
  • 52
  • 6.2.2
  • Top-down System Design
  • Logical libraries and compilation of design units
  • 56
  • 6.2.3
  • Concurrent statements
  • 60
  • 6.2.4
  • A simple pure digital example -- divider
  • 65
  • 6.3
  • Conservative Systems Description
Control code
62363726
Dimensions
25 cm +
Dimensions
4 3/4 in. or 12 cm.
Extent
viii, 291 pages
File format
multiple file formats
Isbn
9780387275857
Isbn Type
(e-book)
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other control number
  • 9780387275840 (HB)
  • 9780387275857 (e-book)
Other physical details
illustrations
Specific material designation
optical disk
System details
System requirements for disc: IBM PC or compatible; Windows; CD-ROM drive, Internet browser

Library Locations

    • Engineering Library & Technology CommonsBorrow it
      W2001 Lafferre Hall, Columbia, MO, 65211, US
      38.946102 -92.330125
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