Coverart for item
The Resource SAT-based scalable formal verification solutions, Malay Ganai, Aarti Gupta

SAT-based scalable formal verification solutions, Malay Ganai, Aarti Gupta

Label
SAT-based scalable formal verification solutions
Title
SAT-based scalable formal verification solutions
Statement of responsibility
Malay Ganai, Aarti Gupta
Creator
Contributor
Subject
Language
eng
Summary
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors' practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products
Member of
Is part of
Cataloging source
GW5XE
http://library.link/vocab/creatorName
Ganai, Malay
Dewey number
621.381548
Illustrations
illustrations
Index
index present
LC call number
TK7874.58
LC item number
.G36 2007eb
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
Gupta, Aarti
Series statement
Series on integrated circuits and systems
http://library.link/vocab/subjectName
  • Integrated circuits
  • TECHNOLOGY & ENGINEERING
  • TECHNOLOGY & ENGINEERING
  • Integrated circuits
  • Informatique
  • Integrated circuits
Label
SAT-based scalable formal verification solutions, Malay Ganai, Aarti Gupta
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Design Verification Challenges -- Design Verification Challenges -- Background -- Basic Infrastructure -- Efficient Boolean Representation -- Hybrid DPLL-Style SAT Solver -- Falsification -- SAT-Based Bounded Model Checking -- Distributed SAT-Based BMC -- Efficient Memory Modeling in BMC -- BMC for Multi-Clock Systems -- Proof Methods -- Proof by Induction -- Unbounded Model Checking -- Abstraction/Refinement -- Proof-Based Iterative Abstraction -- Verification Procedure -- SAT-Based Verification Framework -- Synthesis for Verification
Control code
187015892
Dimensions
unknown
Extent
1 online resource (xxix, 326 pages)
Form of item
online
Isbn
9786610901852
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other physical details
illustrations.
http://library.link/vocab/ext/overdrive/overdriveId
978-0-387-69166-4
Specific material designation
remote
System control number
(OCoLC)187015892
Label
SAT-based scalable formal verification solutions, Malay Ganai, Aarti Gupta
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
  • cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Design Verification Challenges -- Design Verification Challenges -- Background -- Basic Infrastructure -- Efficient Boolean Representation -- Hybrid DPLL-Style SAT Solver -- Falsification -- SAT-Based Bounded Model Checking -- Distributed SAT-Based BMC -- Efficient Memory Modeling in BMC -- BMC for Multi-Clock Systems -- Proof Methods -- Proof by Induction -- Unbounded Model Checking -- Abstraction/Refinement -- Proof-Based Iterative Abstraction -- Verification Procedure -- SAT-Based Verification Framework -- Synthesis for Verification
Control code
187015892
Dimensions
unknown
Extent
1 online resource (xxix, 326 pages)
Form of item
online
Isbn
9786610901852
Media category
computer
Media MARC source
rdamedia
Media type code
  • c
Other physical details
illustrations.
http://library.link/vocab/ext/overdrive/overdriveId
978-0-387-69166-4
Specific material designation
remote
System control number
(OCoLC)187015892

Library Locations

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      38.946102 -92.330125
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