Coverart for item
The Resource System-on-chip test architectures : nanometer design for testability, edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

System-on-chip test architectures : nanometer design for testability, edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

Label
System-on-chip test architectures : nanometer design for testability
Title
System-on-chip test architectures
Title remainder
nanometer design for testability
Statement of responsibility
edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
Contributor
Subject
Language
eng
Summary
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students
Member of
Cataloging source
OPELS
Dewey number
621.39/5
Illustrations
illustrations
Index
index present
LC call number
TK7895.E42
LC item number
S978 2008eb
Literary form
non fiction
Nature of contents
  • dictionaries
  • bibliography
http://library.link/vocab/relatedWorkOrContributorName
  • Wang, Laung-Terng
  • Stroud, Charles E
  • Touba, Nur A
Series statement
The Morgan Kaufmann series in systems on silicon
http://library.link/vocab/subjectName
  • Systems on a chip
  • Integrated circuits
  • Integrated circuits
  • TECHNOLOGY & ENGINEERING
  • TECHNOLOGY & ENGINEERING
  • COMPUTERS
  • Systems on a chip
  • Integrated circuits
  • Integrated circuits
  • Integrated circuits
  • Integrated circuits
  • VLSI
Label
System-on-chip test architectures : nanometer design for testability, edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends
Control code
228148482
Dimensions
unknown
Extent
1 online resource (xxxvi, 856 pages)
Form of item
online
Isbn
9780080556802
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations.
http://library.link/vocab/ext/overdrive/overdriveId
137803:137940
Specific material designation
remote
System control number
(OCoLC)228148482
Label
System-on-chip test architectures : nanometer design for testability, edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
online resource
Carrier category code
cr
Carrier MARC source
rdacarrier
Color
multicolored
Content category
text
Content type code
txt
Content type MARC source
rdacontent
Contents
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends
Control code
228148482
Dimensions
unknown
Extent
1 online resource (xxxvi, 856 pages)
Form of item
online
Isbn
9780080556802
Media category
computer
Media MARC source
rdamedia
Media type code
c
Other physical details
illustrations.
http://library.link/vocab/ext/overdrive/overdriveId
137803:137940
Specific material designation
remote
System control number
(OCoLC)228148482

Library Locations

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