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The Resource Transactions on High-Performance Embedded Architectures and Compilers IV, edited by Per Stenström, (electronic resource)

Transactions on High-Performance Embedded Architectures and Compilers IV, edited by Per Stenström, (electronic resource)

Label
Transactions on High-Performance Embedded Architectures and Compilers IV
Title
Transactions on High-Performance Embedded Architectures and Compilers IV
Statement of responsibility
edited by Per Stenström
Creator
Contributor
Subject
Language
eng
Summary
  • Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008
  • Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008
  • Annotation:
Member of
Is part of
http://library.link/vocab/creatorName
Stenström, Per
Dewey number
004
LC call number
QA76.9.C62
http://library.link/vocab/relatedWorkOrContributorName
SpringerLink (Online service)
Series statement
Lecture Notes in Computer Science,
Series volume
6760
http://library.link/vocab/subjectName
  • Computer science
  • Data transmission systems
  • Logic design
  • Computer Communication Networks
  • Computer Science
  • Arithmetic and Logic Structures
  • Processor Architectures
  • Input/Output and Data Communications
  • Logic Design
  • Computer Communication Networks
  • Programming Languages, Compilers, Interpreters
Summary expansion
Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008
Label
Transactions on High-Performance Embedded Architectures and Compilers IV, edited by Per Stenström, (electronic resource)
Instantiates
Publication
Contents
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation - Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent's Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation - Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent's Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation ? Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent?s Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration
Control code
OCM1bookssj0000611044
Dimensions
unknown
Isbn
9783642245688
Other control number
10.1007/978-3-642-24568-8
Specific material designation
remote
System control number
(WaSeSS)bookssj0000611044
Label
Transactions on High-Performance Embedded Architectures and Compilers IV, edited by Per Stenström, (electronic resource)
Publication
Contents
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation - Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent's Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation - Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent's Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors -- Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces -- Compiler Directed Issue Queue Energy Reduction -- A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors -- Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors -- Special Section on High-Performance and Embedded Architectures and Compilers (HiPEAC) -- A Highly Scalable Parallel Implementation of H.264 -- Communication Based Proactive Link Power Management -- Finding Extreme Behaviors in Microprocessor Workloads -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Special Section on Selected papers from the Workshop on Software and Hardware Challenges of Many-core Platforms -- Transaction Reordering to Reduce Aborts in Software Transactional Memory -- A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture -- A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM -- Software Transactional Memory Validation ? Time and Space Considerations Tiled Multi-Core Stream Architecture -- An Efficient and Flexible Task Management for Many Cores -- Special Section on International Symposium on Systems, ArchitecturesModeling and Simulation -- On Two-layer Brain-inspired Hierarchical Topologies: A Rent?s Rule Approach -- Advanced Packet Segmentation and Buffering Algorithms in Network Processors -- Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation -- A Cost Model for Partial Dynamic Reconfiguration -- Heterogeneous Design in Functional DIF -- Signature-based Calibration of Analytical Performance Models for System-level Design Space Exploration
Control code
OCM1bookssj0000611044
Dimensions
unknown
Isbn
9783642245688
Other control number
10.1007/978-3-642-24568-8
Specific material designation
remote
System control number
(WaSeSS)bookssj0000611044

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