Formal methods in computer-aided design : 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004 ; proceedings, Alan J. Hu, Andrew K. Martin (eds.)

Resource Information

The instance Formal methods in computer-aided design : 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004 ; proceedings, Alan J. Hu, Andrew K. Martin (eds.) represents a material embodiment of a distinct intellectual or artistic creation found in University of Missouri Libraries. This resource is a combination of several types including: Instance, Electronic.

Image

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Label

Formal methods in computer-aided design : 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004 ; proceedings, Alan J. Hu, Andrew K. Martin (eds.)

Title remainder

5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004 ; proceedings

Statement of responsibility

Alan J. Hu, Andrew K. Martin (eds.)

Instantiates

• Formal methods in computer-aided design : 5th International Conference, FMCAD 2004, Austin, Texas, USA, November 15-17, 2004 ; proceedings

Publication

• Berlin, Springer, 2004

Antecedent source

unknown

Bibliography note

Includes bibliographical references and index

Carrier category

online resource

Carrier category code

• cr

Carrier MARC source

rdacarrier

Color

multicolored

Content category

text

Content type code

• txt

Content type MARC source

rdacontent

Contents

Challenges in System-Level Design -- Generating Fast Multipliers Using Clever Circuits -- Verification of Analog and Mixed-Signal Circuits Using Hybrid System Techniques -- A Methodology for the Formal Verification of FFT Algorithms in HOL -- A Functional Approach to the Formal Specification of Networks on Chip -- Proof Styles in Operational Semantics -- Integrating Reasoning About Ordinal Arithmetic into ACL2 -- Combining Equivalence Verification and Completion Functions -- Synchronization-at-Retirement for Pipeline Verification -- Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs -- Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders -- Scalable Automated Verification via Expert-System Guided Transformations -- Simple Yet Efficient Improvements of SAT Based Bounded Model Checking -- Simple Bounded LTL Model Checking -- QuBE++: An Efficient QBF Solver -- Bounded Probabilistic Model Checking with the Mur? Verifier -- Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States -- Bounded Verification of Past LTL -- A Hybrid of Counterexample-Based and Proof-Based Abstraction -- Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis -- Approximate Symbolic Model Checking for Incomplete Designs -- Extending Extended Vacuity -- Parameterized Vacuity -- An Operational Semantics for Weak PSL -- Accepting Predecessors Are Better than Back Edges in Distributed LTL Model-Checking -- Bloom Filters in Probabilistic Verification -- A Simple Method for Parameterized Verification of Cache Coherence Protocols -- A Partitioning Methodology for BDD-Based Verification -- Invariant Checking Combining Forward and Backward Traversal -- Variable Reuse for Efficient Image Computation

Control code

62417235

Dimensions

unknown

Extent

1 online resource (xi, 444 pages)

File format

unknown

Form of item

online

Isbn

9783540304944

Level of compression

unknown

Media category

computer

Media MARC source

rdamedia

Media type code

• c

Other control number

10.1007/b102264

Other physical details

illustrations.

Quality assurance targets

not applicable

Record ID

.b13009111x

Reformatting quality

unknown

Sound

unknown sound

Specific material designation

remote

System control number

(OCoLC)62417235