Hardware specification, verification, and synthesis : Mathematical aspects : proceedings
Resource Information
The work Hardware specification, verification, and synthesis : Mathematical aspects : proceedings represents a distinct intellectual or artistic creation found in University of Missouri Libraries. This resource is a combination of several types including: Work, Language Material, Books, http://bibfra.me/vocab/marc/conference-publication.
The Resource
Hardware specification, verification, and synthesis : Mathematical aspects : proceedings
Resource Information
The work Hardware specification, verification, and synthesis : Mathematical aspects : proceedings represents a distinct intellectual or artistic creation found in University of Missouri Libraries. This resource is a combination of several types including: Work, Language Material, Books, http://bibfra.me/vocab/marc/conference-publication.
- Label
- Hardware specification, verification, and synthesis : Mathematical aspects : proceedings
- Title remainder
- Mathematical aspects : proceedings
- Statement of responsibility
- M. Leeser, G. Brown (eds.) ; Mathematical Sciences Institute workshop, Cornell University Ithaca, New York, USA, July 5-7, 1989 proceedings
- Subject
-
- Conference papers and proceedings
- Integrated circuits -- Verification
- Integrated circuits -- Verification
- Integrated circuits -- Verification -- Congresses
- Integrated circuits -- Very large scale integration | Design and construction | Data processing
- Integrated circuits -- Very large scale integration | Design and construction | Data processing
- Integrated circuits -- Very large scale integration | Design and construction | Data processing -- Congresses
- Conference papers and proceedings
- Language
- eng
- Summary
- Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States
- Cataloging source
- SCPER
- Dewey number
- 621.39/5
- Illustrations
- illustrations
- Index
- no index present
- LC call number
- TK7874
- LC item number
- .C685 1989
- Literary form
- non fiction
- Nature of contents
-
- dictionaries
- bibliography
- Series statement
- Lecture notes in computer science,
- Series volume
- 408
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