Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds

Resource Information

The instance Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds represents a material embodiment of a distinct intellectual or artistic creation found in University of Missouri Libraries. This resource is a combination of several types including: Instance, Electronic.

Image

http://images.btol.com/ContentCafe/Jacket.aspx?UserID=ebsco-test&Password=ebsco-test&Return=T&Value=9783540409229&Type=L

Label

Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds

Title remainder

third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings

Statement of responsibility

Warren A. Hunt, Jr., Steven D. Johnson, eds

Instantiates

• Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, TX, USA, November 1-3, 2000 : proceedings

Publication

• Berlin | New York, Springer, 2000

Bibliography note

Includes bibliographical references and index

Carrier category

online resource

Carrier category code

• cr

Carrier MARC source

rdacarrier

Content category

text

Content type code

• txt

Content type MARC source

rdacontent

Contents

Applications of Hierarchical Verification in Model Checking -- Applications of Hierarchical Verification in Model Checking -- Invited Talk -- Trends in Computing -- Invited Paper -- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor -- Contributed Papers -- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps -- Automated Refinement Checking for Asynchronous Processes -- Border-Block Triangular Form and Conjunction Schedule in Image Computation -- B2M: A Semantic Based Tool for BLIF Hardware Descriptions -- Checking Safety Properties Using Induction and a SAT-Solver -- Combining Stream-Based and State-Based Verification Techniques -- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles -- Correctness of Pipelined Machines -- Do You Trust Your Model Checker? -- Executable Protocol Specification in ESL -- Formal Verification of Floating Point Trigonometric Functions -- Hardware Modeling Using Function Encapsulation -- A Methodology for the Formal Analysis of Asynchronous Micropipelines -- A Methodology for Large-Scale Hardware Verification -- Model Checking Synchronous Timing Diagrams -- Model Reductions and a Case Study -- Modeling and Parameters Synthesis for an Air TrafficManagement System -- Monitor-Based Formal Specification of PCI -- SAT-Based Image Computation with Application in Reachability Analysis -- SAT-Based Verification without State Space Traversal -- Scalable Distributed On-the-Fly Symbolic Model Checking -- The Semantics of Verilog Using Transition System Combinators -- Sequential Equivalence Checking by Symbolic Simulation -- Speeding Up Image Computation by Using RTL Information -- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs -- Symbolic Simulation with Approximate Values -- A Theory of Consistency for Modular Synchronous Systems -- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods -- Visualizing System Factorizations with Behavior Tables

Control code

619611810

Dimensions

unknown

Extent

1 online resource (xi, 537 pages)

Form of item

online

Isbn

9783540409229

Media category

computer

Media MARC source

rdamedia

Media type code

• c

Other control number

10.1007/3-540-40922-X

Other physical details

illustrations.

Record ID

.b130098887

Specific material designation

remote

System control number

(OCoLC)619611810